1. Field of the Invention
This invention relates generally to digital signal processing and specifically to the implementation of a dynamically re-configurable decimation system in various digital devices, including programmable logic devices.
2. Description of Related Art
Many digital signal processing devices use decimation to condition input data for various reasons. Decimation, or downsampling, of a signal reduces the number of data points in the original data signal, typically to permit use of the data at a lower data rate. Decimation is used in a variety of digital signal processing devices in a wide range of applications (for example, medical imaging).
In its simplest implementation, data rate decimation can be performed by merely removing original data points to achieve a desired reduced data rate. For example, in FIG. 1, an original signal 51 having data points 50 in FIG. 1a can be decimated by a factor of 2 by merely “deleting” every other data point 50, yielding the decimated signal 52 in FIG. 1b. While this technique might be sufficiently accurate in some applications requiring less precision, the decimated signal typically loses important information contained in the deleted data points. This is especially true where larger decimation factors are used, as seen in the example of FIG. 1c, where the original signal 51 of FIG. 1a has been decimated by a factor of 5 by keeping only every fifth data point to yield signal 55. A comparison of signal 51 and signal 55 shows that intermediate, deleted data points should have an effect on or be taken into consideration in producing the decimated signal 55. However, the simple deletion of data points fails to do this.
One technique for more accurately portraying an original signal after decimation is the use of polyphase decomposition. Polyphase decomposition uses basic finite impulse response (FIR) filtering to remove noise and take into account contextual data information contained in an original signal that is being decimated. A more desirable signal decimation than mere deletion of data points and/or values is achievable using a standard decimation technique, as shown in FIG. 2a. To decimate a signal, a low-pass filter is applied at 61, which removes spectral components that are not present at the targeted lower sample rate. After filtering, appropriate data points of the conditioned signal can be deleted at 62. This process is seen as applied to the data points 70 of an original signal 71 in FIG. 2b. After appropriate filtering in FIG. 2c, the data has been conditioned for decimation of the signal in FIG. 2d. 
The decimation shown in FIG. 2 can be performed by typical polyphase decomposition. Such decimation techniques are explained in detail in Altera Application Note 73 (ver. 1.01, February 1998) and the Altera FIR Compiler Megafunction User Guide (ver. 2.6, October 2002), which both are incorporated herein by reference in their entireties for all purposes. In such a decimation system, a commutator cyclically delivers data to the input of each polyphase filter in the decimation system. The filters store or have access to coefficients that are calculated to condition the incoming signal's data to achieve the desired output signal characteristics for a fixed, reduced data rate (for example, removing the undesirable frequency components of the signal prior to decimation). These coefficients are multiplied by the appropriate data value and the outputs of the filters are the data/coefficient products, which are fed to an adder. The final data values are the sums of the data/coefficient products. Polyphase decimation filters provide speed optimization because each filter runs at the output data rate.
A programmable logic device (“PLD”) is a programmable integrated circuit that allows the user of the circuit, using software control, to program the PLD to perform particular logic functions. A wide variety of these devices are manufactured by Altera Corporation of San Jose, Calif. The basic structure and operation of PLDs are well known to those of ordinary skill in the art. Logic functions performed by small, medium, and large-scale integration integrated circuits can instead be performed by programmable logic devices. When an integrated circuit manufacturer supplies a typical programmable logic device, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform a particular function or functions required by the user's application. The PLD then can function in a larger system designed by the user just as though dedicated logic chips were employed.
Many applications require multiple decimation rates due, for example, to changing conditions within a digital signal processing environment. In cases where different decimation rates are required and/or desirable, hardware-based structures have been used to implement all of the desired decimation rates. Such structures are frequently undesirable due to their large size (using substantial resources in the digital signal processing device) and slow operation. These digital signal processing devices typically implement separate decimation systems for each decimation rate needed by the user.
FIR filters have been implemented in PLDs as part of digital signal processing systems to perform signal preconditioning, anti-aliasing, band selection, decimation/interpolation, low-pass filtering and video convolution functions. PLDs are flexible, high-performance devices that can easily implement FIR filters. For example, a PLO can be used for one or more critical filtering functions in a digital signal processing (DSP) microprocessor-based application, freeing the DSP processor to perform the lower-bit-rate, algorithmically complex operations. A DSP microprocessor can implement an 8-tap FIR filter at 5 million samples per second (MSPS), while an off-the-shelf FIR filter circuit can deliver 30 MSPS. In contrast, PLDs such as those manufactured by Altera. Corp. can implement the same filter at over 100 MSPS. The coefficients of a FIR filter can be calculated and/or generated in various ways. For example, one can use the FIR compiler that is the subject of U.S. application Ser. No. 09/773,853, filed Jan. 31, 2001, and assigned to Altera Corp., which is incorporated herein by reference in its entirety for all purposes. Coefficients also can be created using other applications such as MATLAB. The calculation and generation of coefficients by different types of coefficient generators is known to those skilled in the art.
A conventional FIR filter is a weighted tapped delay line. The filter design process involves identifying coefficients that will yield the frequency response specified for the particular system for which the FIR filter is being designed. The signal frequencies that pass through the filter can be modified simply by changing the values of the coefficients or by adding more coefficients.
Digital signal processors with a limited number of multiplier-accumulators require many clock cycles to compute each output value because the number of cycles is directly related to the order of the filter. A dedicated hardware solution can achieve one output per clock cycle. In contrast, a fully parallel, pipelined FIR filter implemented in a PLD can be operated at data rates above 100 MSPS, making PLDs ideal for high-speed filtering applications.
Systems, methods and techniques that permit a range of decimation rates and factors (that is, data rate reductions), while efficiently using area, speed and other resources in a PLD or other digital signal processing device would represent a significant advancement in the art. Moreover, generating a flexible structure, using a single, fixed hardware structure, to implement a variety of decimating FIR filters whose rates can be dynamically changed at run time would likewise constitute a significant advancement in the art.